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d a t a sh eet product speci?cation supersedes data of 2000 aug 29 file under integrated circuits, ic02 2000 nov 09 integrated circuits tda8007b double multiprotocol ic card interface
2000 nov 09 2 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b features control and communication through an 8-bit parallel interface, compatible with multiplexed or non-multiplexed memory access specific iso uart with parallel access on i/o for automatic convention processing, variable baud rate through frequency or division ratio programming, error management at character level for t = 0, extra guard time register 1 to 8 characters fifo in reception mode parity error counter in reception mode dual v cc generation (5 v 5%, 65 ma (max.) or 3 v 8%, 50 ma (max.) with controlled rise and fall times) dual cards clock generation (up to 10 mhz), with two times synchronous frequency doubling cards clock stop high, clock stop low or 1.25 mhz (from internal oscillator) for cards power-down mode automatic activation and deactivation sequence through an independent sequencer supports the asynchronous protocols t = 0 and t = 1 in accordance with iso 7816 and emv versatile 24-bit time-out counter for answer to reset (atr) and waiting times processing 22 elementary time unit (etu) counter for block guard time (bgt) supports synchronous cards current limitations in the event of short-circuit special circuitry for killing spikes during power-on/-off supply supervisor for power-on/-off reset step-up converter (supply voltage from 2.7 to 6 v), doubler, tripler or follower according to v cc and v dd additional i/o pin allowing use of the iso uart for another analog interface (pin i/oaux) additional interrupt pin allowing detection of level toggling on an external signal (pin intaux) fast and efficient swapping between the 3 cards due to separate buffering of parameters for each card chip select input allowing use of several devices in parallel and memory space paging enhanced esd protections on card side [6 kv (min.)] software library for easy integration within the application power-down mode for reducing current consumption when no activity. applications multiple smart card readers for multiprotocol applications (emv banking, digital pay tv, access control, etc.). general description the tda8007b is a low cost card interface for dual smart card readers. controlled through a parallel bus, it takes care of all iso 7816, emv and gsm11-11 requirements. it may be interfaced to the p0/p2 ports of a 80c51 family microcontroller, and be addressed as a memory through movx instructions. it may also be addressed on a non-multiplexed 8-bit data bus, by means of address registers ad0, ad1, ad2 and ad3. the integrated iso uart and the time-out counters allow easy use even at high baud rates with no real time constraints. due to its chip select and external i/o and int features, it greatly simplifies the realization of any number of cards readers. it gives the cards and the reader a very high level of security, due to its special hardware against esd, short-circuiting, power failure, etc. its integrated step-up converter allows operation within a supply voltage range of 2.7 to 6 v. a software library has been developed, taking care of all actions required for t = 0, t = 1 and synchronous protocols (see application reports). ordering information type number package name description version TDA8007BHL lqfp48 plastic low pro?le quad ?at package; 48 leads; body 7 7 1.4 mm sot313-2
2000 nov 09 3 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b quick reference data symbol parameter conditions min. typ. max. unit v dd supply voltage 2.7 - 6v i dd(pd) supply current in power-down mode v dd = 3.3 v; cards inactive; xtal oscillator stopped -- 350 m a v dd = 3.3 v; cards active at v cc = 5 v; clk stopped; xtal oscillator stopped -- 3ma i dd(sm) supply current in sleep mode cards powered at 5 v but clock stopped -- 5.5 ma i dd(om) supply current in operating mode v dd = 3.3 v; f xtal = 20 mhz; v cc1 =v cc2 =5v; i cc1 +i cc2 =80ma -- 315 ma v cc output card supply voltage including static loads (5 v card) 4.75 5.0 5.25 v with 40 nc dynamic loads on 200 nf capacitor (5 v card) 4.6 - 5.4 v including static loads (3 v card) 2.78 - 3.22 v with 24 nc dynamic loads on 200 nf capacitor (3 v card) 2.75 - 3.25 v i cc output card supply current operating; 5 v card -- 65 ma operating; 3 v card -- 50 ma overload detection - 100 - ma i cc1 +i cc2 sum of both cards currents -- 80 ma sr slew rate on v cc (rise and fall) c l(max) = 300 nf 0.05 0.16 0.22 v/ m s t deact deactivation cycle duration -- 150 m s t act activation cycle duration -- 225 m s f xtal crystal frequency 4 - 27 mhz f op operating frequency external frequency applied to pin xtal1 0 - 25 mhz t amb ambient temperature - 25 - +85 c
2000 nov 09 4 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b block diagram handbook, full pagewidth analog drivers and sequencers iso7816 uart interface control clock circuit step-up converter v dd gnd sap sam v dda agnd v up delay rstout int ale ad0 ad1 ad2 ad3 rd wr d0 d1 d2 d3 d4 d5 d6 d7 cs i/oaux intaux xtal1 xtal2 c41 1 48 40 39 45 44 43 42 36 37 28 29 30 31 32 33 34 35 38 2 41 47 46 15 13 11 17 18 16 12 14 7 5 3 9 10 8 4 6 20 25 24 22 26 21 23 19 27 clk1 c81 rst1 v cc1 pres1 i/o1 gndc1 c42 clk2 c82 rst2 v cc2 pres2 i/o2 gndc2 100 nf supply and supervisor int osc tda8007b xtal osc fce534 220 nf 220 nf 22 nf sbp sbm 220 nf time-out counter fig.1 block diagram.
2000 nov 09 5 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b pinning symbol pin description rstout 1 open-drain output for resetting external chips i/oaux 2 input or output for an i/o line issued of an auxiliary smart card interface i/o1 3 data line to/from card 1 (iso c7 contact) c81 4 auxiliary i/o for iso c8 contact (synchronous cards for instance) for card 1 pres1 5 card 1 presence contact input (active high or low by mask option) c41 6 auxiliary i/o for iso c4 contact (synchronous cards for instance) for card 1 gndc1 7 ground for card 1 clk1 8 clock output to card 1 (iso c3 contact) v cc1 9 card 1 supply output voltage (iso c1 contact) rst1 10 card 1 reset output (iso c2 contact) i/o2 11 data line to/from card 2 (iso c7 contact) c82 12 auxiliary i/o for iso c8 contact (synchronous cards for instance) for card 2 pres2 13 card 2 presence contact input (active high or low by mask option) c42 14 auxiliary i/o for iso c4 contact (synchronous cards for instance) for card 2 gndc2 15 ground for card 2 clk2 16 clock output to card 2 (iso c3 contact) v cc2 17 card 2 supply output voltage (iso c1 contact) rst2 18 card 2 reset output (iso c2 contact) gnd 19 ground connection v up 20 output of the step-up converter sap 21 contact 1 for the step-up converter (connect a low esr 220 nf capacitor between pins sap and sam) sbp 22 contact 3 for the step-up converter (connect a low esr 220 nf capacitor between pins sbp and sbm) v dda 23 positive analog supply voltage for the step-up converter sbm 24 contact 4 for the step-up converter (connect a low esr 220 nf capacitor between pins sbp and sbm) agnd 25 ground connection for the step-up converter sam 26 contact 2 for the step-up converter (connect a low esr 220 nf capacitor between pins sap and sam) v dd 27 positive supply voltage d0 28 data 0 or add 0 d1 29 data 1 or add 1 d2 30 data 2 or add 2 d3 31 data 3 or add 3 d4 32 data 4 or add 4 d5 33 data 5 or add 5 d6 34 data 6 or add 6 d7 35 data 7 or add 7 rd 36 read selection signal (read or write in non-multiplexed con?guration)
2000 nov 09 6 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b wr 37 write selection signal (enable in case of non-multiplexed con?guration) cs 38 chip select input (active high or low) ale 39 address latch enable in case of multiplexed con?guration (connect to v dd in non-multiplexed con?guration) int 40 interrupt output (active low) intaux 41 auxiliary interrupt input ad3 42 register selection address 3 ad2 43 register selection address 2 ad1 44 register selection address 1 ad0 45 register selection address 0 xtal2 46 connection pin for an external crystal xtal1 47 connection pin for an external crystal or input for an external clock signal delay 48 connection pin for an external delay capacitor symbol pin description handbook, full pagewidth TDA8007BHL fce678 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 delay xtal1 xtal2 ad0 ad1 ad2 ad3 intaux int ale cs wr pres2 c42 gndc2 clk2 v cc2 rst2 gnd v up sap sbp v dda sbm rstout i/oaux i/o1 c81 pres1 c41 gndc1 clk1 v cc1 rst1 i/o2 c82 rd d7 d6 d5 d4 d3 d2 d1 d0 v dd sam agnd fig.2 pin configuration.
2000 nov 09 7 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b functional description throughout this specification, it is assumed that the reader is aware of iso 7816 norm terminology. interface control the tda8007b can be controlled via an 8-bit parallel bus (bits d0 to d7). if a microcontroller with a multiplexed address/data bus (such as the 80c51) is used, then d0 to d7 may be directly connected to p0 to p7. when cs is low, the demultiplexing of address and data is performed internally using the ale signal, a low pulse on pin rd allows the selected register to be read, a low pulse on pin wr allows the selected register to be written to. the tda8007b automatically switches to the multiplexed bus configuration if a rising edge is detected on pin ale. in this event, ad0 to ad3 play no role and may be tied to v dd or gnd. using a 80c51 microcontroller, the tda8007b is simply controlled with movx instructions. if ale is tied to v dd or gnd, then the tda8007b will be in the non-multiplexed configuration. in this case, the address bits are external pins ad0 to ad3, rd is the read/ write control signal, and wr is a data write or read active low enable signal. in both configurations, the tda8007b is selected only when cs is low. int is an active low interrupt signal. in non-multiplexed bus configuration, cs and en play the same role. in read operations (rd/ wr is high), the data corresponding to the chosen address is available on the bus when both cs and en are low. in write operations, the data present on the bus is written when signals rd/ wr, cs and en become low. handbook, full pagewidth latch mux mux addresses fce679 rd wr rec cs ad0 to ad3 ale wr rd d0 to d7 registers fig.3 multiplexed bus recognition.
2000 nov 09 8 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b handbook, full pagewidth ale cs d0 to d7 rd wr fce680 t w(ale) t avll t avll address data read address data write t (rwh-ah) t (rwh-ah) t w(rd) t (dv-wl) t (al-rwl) t (al-rwl) t (rl-dv) t w(wr) fig.4 control with multiplexed bus. handbook, full pagewidth ad0 to ad3 rd en d0 to d7 fce681 t (reh-cl) t (reh-cl) t (cel-dv) t (ceh-dz) t (ad-dv) t (rl-cel) data out read read read write (data written on falling edge of cs) data out data out data in cs t (crel-dz) t (cel-dv) t (ceh-dz) fig.5 control with non-multiplexed bus.
2000 nov 09 9 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b control registers the tda8007b has 2 complete analog interfaces which can drive card 1 and card 2. the data to and from these 2 cards share the same iso uart. the data to and from a third card (card 3), externally interfaced (with a tda8002 or tda8003 for example), may also share the same iso uart. cards 1, 2 and 3 have dedicated registers for setting the parameters of the iso uart; programmable divider register (pdr), guard time register (gtr), uart configuration register 1 (ucr1), uart configuration register 2 (ucr2) and clock configuration register (ccr). cards 1 and 2 also have dedicated registers for controlling their power and clock configuration. the power control register (pcr) for card 3, is controlled externally. the pcr is also used for writing or reading on the auxiliary card contacts c4 and c8. card 1, 2 or 3 can be selected via the card select register (csr). when one card is selected, the corresponding parameters are used by the iso uart. the csr also contains one bit for resetting the iso uart (active low). this bit is reset after power-on, and must be set to high before starting with any one of the cards. it may be reset by software when necessary. when the specific parameters of the cards have been programmed, the uart may be used with the following registers: uart receive register (urr), uart transmit register (utr), uart status register (usr) and mixed status register (msr). in reception mode, a fifo of 1 to 8 characters may be used, and is configured with the fifo control register (fcr). the hardware status register (hsr) gives the status of the supply voltage, of the hardware protections and of the card movements. hsr and usr give interrupts on pin int when some of their bits have been changed. the msr does not give interrupts and may be used in the polling mode for some operations; for this use, some of the interrupt sources within the usr and hsr may be masked. a 24-bit time-out counter may be started to give an interrupt after a number of etus programmed into registers tor1, tor2 and tor3. this will help the microcontroller in processing different real-time tasks (atr, wwt, bwt, etc.) mainly if the microcontrollers and cards clock are asynchronous. this counter is configured with a register time-out counter configuration (toc). it may be used as a 24-bit or as a 16 + 8 bits. each counter can be set to start counting once data has been written, or on detection of a start bit on the i/o, or as auto-reload.
2000 nov 09 10 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... handbook, full pagewidth program divider register 2 card2 guard time register 2 uart configuration register 21 uart configuration register 22 time-out register 1 general card select register hard status register time-out register 2 time-out register 3 uart transmit register iso uart uart status register mixed status register uart receive register fifo control register time-out configuration clock configuration register 2 power control register 2 program divider register 3 card3 guard time register 3 uart configuration register 31 uart configuration register 32 clock configuration register 3 fce682 program divider register 1 card1 guard time register 1 uart configuration register 11 uart configuration register 12 clock configuration register 1 power control register 1 fig.6 registers summary.
2000 nov 09 11 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b g eneral registers the card select register (see table 1) is used for selecting the card on which the uart will act, and also to reset the iso uart. if sc1 = 1, then card 1 is selected; if sc2 = 1, then card 2 is selected, if sc3 = 1, then card 3 is selected. these bits must be set one at a time. after reset, card 1 is selected by default. the bit reset iso uart ( riu) must be set to logic 1 by software before any action on the uart can take place. when reset, this bit resets all uart registers to their initial value. it should be noted that access to card 3 is only possible once either card 1 or 2 has been activated. the hardware status register (see table 2) gives the status of the chip after a hardware problem has been detected. presence latch 1 (prl1) and presence latch 2 (prl2) are high when a change has occurred on pr1 and pr2. supervisor latch (supl) is high when the supervisor has been activated. protection 1 (prtl1) and protection 2 (prtl2) are high when a default has been detected on card readers 1 and 2. (prtl is the or function of protection on v cc and rst). ptl is set if overheating has occurred. intauxl is high if the level on the intaux input has been changed. when prtl2, prtl1, prl2 or prl1 or ptl is high, then int is low. the bits having caused the interrupt are cleared when the hsr has been read-out. the same occurs with bit intauxl if not disabled. at power-on, or after a supply voltage dropout, supl is set and int is low. int will return high at the end of the alarm pulse on pin rstout. supl will be reset only after a status register read-out outside the alarm pulse (see fig.7). in case of emergency deactivation (by prtl1, prtl2, supl, prl2, prl1 or ptl), the start bit is automatically reset by hardware. the three registers tor1, tor2 and tor3 form a programmable 24-bit etu counter, or two independant counters (one 16-bit and one 8-bit). the value to load in tor1, 2 and 3 is the number of etus to count. the toc register is used for setting different configurations of the time-out counter as given in table 7 (all other configurations are undefined). table 1 card select register (write and read); address: 0 (all signi?cant bits are cleared after reset, except for sc1 which is set) table 2 hardware status register (read only); address: f (all signi?cant bits are cleared after reset, except for supl which is set within the rstout pulse) table 3 time-out register 1 (write only); address: 9 (all bits are cleared after reset) table 4 time-out register 2 (write only); address: a (all bits are cleared after reset) cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 not used not used not used not used riu sc3 sc2 sc1 hs7 hs6 hs5 hs4 hs3 hs2 hs1 hs0 not used prtl2 prtl1 supl prl2 prl1 intauxl ptl to17 to16 to15 to14 to13 to12 to11 to10 tol7 tol6 tol5 tol4 tol3 tol2 tol1 tol0 to27 to26 to25 to24 to23 to22 to21 to20 tol15 tol14 tol13 tol12 tol11 tol10 tol9 tol8
2000 nov 09 12 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b table 5 time-out register 3 (write only); address: b (all bits are cleared after reset) table 6 time-out con?guration register (read and write); address: 8 (all bits are cleared after reset) table 7 time-out counter con?gurations to37 to36 to35 to34 to33 to32 to31 to30 tol23 tol22 tol21 tol20 tol19 tol18 tol17 tol16 toc7 toc6 toc5 toc4 toc3 toc2 toc1 toc0 toc7 toc6 toc5 toc4 toc3 toc2 toc1 toc0 toc operating mode 00 all counters are stopped 61 counter 1 is stopped, and counters 3 and 2 form a 16-bit counter. counting the value stored in tor3 and tor2 is started after 61 is written in the toc. an interrupt is given, and bit to3 is set within the usr when the terminal count is reached. the counter is stopped by writing 00 in the toc. 65 counter 1 is an 8-bit auto reload counter, and counters 3 and 2 form a 16-bit counter. counter 1 starts counting the content of tor1 on the ?rst start bit (reception or transmission) detected on i/o after 65 is written in the toc. when counter 1 reaches its terminal count, an interrupt is given, bit to1 in the usr is set, and the counter automatically restarts the same count until it is stopped. it is not allowed to change the content of tor1 during a count. in this mode, the accuracy of counter 1 is 0.5 etu. counters 3 and 2 are wired as a single 16-bit counter and starts counting the value tor3 and tor2 when 65 is written in the toc. when the counter reaches its terminal count, an interrupt is given and bit to3 is set within the usr. both counters are stopped when 00 is written in the toc. 68 counters 3, 2 and 1 are wired as a single 24-bit counter. counting the value stored in tor3, tor2 and tor1 is started after 68 is written in the toc. the counter is stopped by writing 00 in the toc. it is not allowed to change the content of tor3, tor2 and tor1 within a count. 7c counters 3, 2 and 1 are wired as a single 24-bit counter. counting the value stored in tor3, tor2 and tor1 on the ?rst start bit detected on i/o (reception or transmission) after the value has been written. it is possible to change the content of tor3, tor2 and tor1 during a count; the current count will not be affected and the new count value will be taken into account at the next start bit. the counter is stopped by writing 00 in the toc. in this con?guration tor3, tor2 and tor1 must not be all zero. e5 same con?guration as toc = 65, except that counter 1 will be stopped at the end of the 12th etu following the ?rst start bit detected after e5 has been written in the toc.
2000 nov 09 13 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b the time-out counter is very useful for processing the clock counting during atr, the work waiting time, or the waiting times defined in t = 1 protocol. it should be noted that the 200 and 400 clk counter used during atr is done by hardware when the start session is set; a specific hardware controls functionality bgt in t = 1 protocol, and a specific register is available for processing the extra guard time. the possible use of the counters is as follows: atr (cold reset): C before activation; tor1 = c0h, tor2 = 6eh, tor3 = 0 and toc = 65. once activated, timer 2 + 3 will count 40920 clock pulses before giving an interrupt. C on interrupt; tor2 = 76h and toc = 65. if a character is received from the card before the timeout, then counter 1 will be enabled. counter 1 will give one interrupt every 192 etus, so the software will count 100 times to verify that the atr is finished before 19200 etus. the uart will give an interrupt with bit buffer full (bf) at 10.5 etus after the start bit. C on interrupt; tor3 = 25h, tor2 = 80h and toc = 65. counter 1 keeps on counting 100 192 etus, while counter 2 and 3 counts 9600 etus. this sequence is repeated until the character before the last one of the atr. C on interrupt tor3 = 25h, tor2 = 80h and toc = e5. timer 1 will be automatically stopped at the end of the last character of the atr, allowing a count of 19200 etus. C on interrupt toc = 00. work waiting time (wwt) in t = 0 protocol; C before sending the first command to the card tor1, tor2 and tor3 should be loaded with the correct 960 wi d value and toc = 7c C timer 3, 2 and 1 will count the wwt between each start bit character waiting time (cwt) and block waiting time (bwt) in t = 1 protocol: C before sending the first block to the card, tor3, tor2 and tor1 should be loaded with the cwt and toc=7c C timer 3 + 2 + 1 will count the cwt between each start bit C before the end of the block, tor3, tor2 and tor1 should be loaded with the bwt C time r3+2+1 will count the bwt from the last start bit of the sent block C after reception of the first character of the block from the card, tor3, tor2 and tor1 should be loaded with the cwt C time r3+2+1 will count the cwt between each received start bit C and so on. before and after clock stop (example, where etu = 372 clock pulses): C after the last received character on i/o, tor3 = 0, tor2 = 6 and toc = 61 C time r3+2 will start counting 2232 clock pulses before giving an interrupt C on interrupt, the software may stop the clock to the card C when it is necessary to restart the clock, tor3 = 0, tor2 = 2, toc = 61 and restart the clock C time r3+2 gives an interrupt at 744 clock pulses, and then the software can send the first command to the card. iso uart registers when the microcontroller wants to transmit a character to the selected card, it writes the data in direct convention in the uart transmit register (see table 8). the transmission: starts at the end of writing (on the rising edge of wr) if the previous character has been transmitted and if the extra guard time has expired; or starts at the end of the extra guard time if this one has not expired; or does not start if the transmission of the previous character is not completed. in the case of a synchronous card (bit san within ucr2 is set), only d0 is relevant, and is copied on the i/o of the selected card. when the microcontroller wants to read data from the card it reads it from the uart receive register (see table 9) in direct convention. in case of a synchronous card, only d0 is relevant and is a copy of the state of the selected card i/o. when needed, this register may be tied to a fifo whose length n is programmable between 1 and 8. if n > 1, then no interrupt is given until the fifo is full. the microcontroller may empty the fifo at any time.
2000 nov 09 14 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b error management in protocol: t=0: in the event of a parity error, the received byte is not stored in the fifo, and the error counter is incremented. the error counter is programmable between 1 and 8. when the programmed number is reached, bit pe is set in the status register usr and int goes low. the error counter must be reprogrammed to the desired value after its count has been reached. t=1: in the event of a parity error, the character is loaded in the fifo, and bit pe is set whatever the programmed value in parity error counter. when the fifo is full, bit rbf in the status register usr is set. this bit is reset when at least one character has been read from the urr. when the fifo is empty, bit fe is set as long as no character has been received. the mixed status register (see table 10) relates the status of pin intaux, the cards presence contacts pr1 and pr2, the bgt counter, the fifo empty indication and the transmit/receive ready indicator tbe/rbf. bit intaux is set when the level on pin intaux is high, it is reset when the level is low. bit bgt is linked with a 22 etu counter, which is started at every start bit on the i/o. bit bgt is set if the count is finished before the next start bit. this helps to verify that the card has not answered before 22 etus after the last transmitted character, or not transmitting a character before 22 etus after the last received character. pr1 is high when card 1 is present, pr2 is high when card 2 is present. fe is set when the reception fifo is empty. it is reset when at least one character has been loaded in the fifo. bit tbe/rbf (transmit buffer empty/receive buffer full) is set when: changing from reception mode to transmission mode a character has been transmitted by the uart the reception fifo is full. bit tbe/rbf is reset after power-on or after one of the following: when bit riu is reset when a character has been written to the utr when at least one character has been read in the fifo when changing from transmission mode to reception mode. no bits within the msr act upon int: the fifo control register bits are given in table 11, fl2, fl1 and fl0 determine the depth of the fifo (000 = length 1, 111 = length 8). pec2, pec1 and pec0 determine the number of parity errors before setting bit pe in the usr and pulling int low; 000 indicates that if only one parity error has occurred, bit pe is set; 111 indicates that bit pe will be set after 8 parity errors. pec2, pec1 and pec0 need to be reprogrammed to the desired value after bit pe has been set. in protocol t = 0: if a correct character is received before the programmed error number is reached the error counter will be reset. if the programmed number of allowed parity errors is reached, bit pe in the usr will be set as long as the usr has not been read. in protocol t = 1: the error counter has no action (bit pe is set at the first wrong received character). the uart status register (see table 12) is used by the microcontroller to monitor the activity of the iso uart and that of the time-out counter. transmission buffer empty (tbe) is high when the uart is in transmission mode, and when the microcontroller may write the next character to transmit in the utr. it is reset when the microcontroller has written data in the transmit register or when bit t/r within ucr1 has been reset either automatically or by software. after detection of a parity error in transmission, it is necessary to wait 13 etus before rewriting the character which has been not acknowledged (nak) by the card. reception buffer full (rbf) is high when the fifo is full. the microcontroller may read some of the characters in the urr, which clears bit rbf. tbe and rbf share the same bit within the usr (when in transmission mode, the relevant bit is tbe; when in reception mode, it is rbf). framing error (fer) is high when the i/o was not in the high-impedance state at 10.25 etus after a start bit. it is reset when the usr has been read-out.
2000 nov 09 15 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b overrun (ovr) is high if the uart has received a new character whilst the fifo was full. in this case, at least one character has been lost. in protocol t = 0: parity error (pe) is high if the uart has detected a number of received characters with parity errors equal to the number written in pec2, pec1 and pec0 or if a transmitted character has been naked by the card. in protocol t = 0: a character received with a parity error is not stored in the fifo (the card is supposed to repeat this character). in protocol t = 1: a character with a parity error is stored in the fifo and the parity error counter is not active. early answer (ea) is high if the first start bit on the i/o during atr has been detected between 200 and 384 clk pulses (all activities on the i/o during the 200 first clk pulses with rst low or high are not taken into account). these 2 features are reinitialized at each toggling of rst. bit to1 is set when counter 1 has reached its terminal count. bit to3 is set when counter 3 has reached its terminal count. if any of the status bits fer, ovr, pe, ea, to1 or to3 are set then int will go low. the bit having caused the interrupt is reset at the end of a read operation of the usr. if tbe/rbf is set, and if the mask bit distbe/rbf within usr2 is not set, then int will also be low. tbe/rbf is reset when data has been written to the utr, when data has been read from the urr, or when changing from transmission mode to reception mode. table 8 uart transmit register (write only); address: d (all bits are cleared after reset) table 9 uart receive register (read only); address: d (all bits are cleared after reset) table 10 mixed status register (read only); address: c (bits tbe, rbf and bgt are cleared after reset; bit fe is set after reset) table 11 fifo control register (write only); address: c (all relevant bits are cleared after reset) table 12 uart status register (read only); address: e (all bits are cleared after reset) ut7 ut6 ut5 ut4 ut3 ut2 ut1 ut0 ut7 ut6 ut5 ut4 ut3 ut2 ut1 ut0 ur7 ur6 ur5 ur4 ur3 ur2 ur1 ur0 ur7 ur6 ur5 ur4 ur3 ur2 ur1 ur0 ms7 ms6 ms5 ms4 ms3 ms2 ms1 ms0 not used fe bgt not used pr2 pr1 intaux tbe/rbf fc7 fc6 fc5 fc4 fc3 fc2 fc1 fc0 not used pec2 pec1 pec0 not used fl2 fl1 fl0 us7 us6 us5 us4 us3 us2 us1 us0 to3 not used to1 ea pe ovr fer tbe/rbf
2000 nov 09 16 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b c ard registers when cards 1 2 or 3 are selected, then the following registers may be used for programming some specific parameters. the programmable divider register (see table 13) is used for counting the cards clock cycles forming the etu. it is an auto-reload 8-bit counter decounting from the programmed value down to 0. table 13 programmable divider register (pdr1, 2 and 3) (read and write); address: 2 (all bits are cleared after reset) the uart configuration register 2 bits are given in table 14. if bit psc is set to logic 1, then the prescaler value is 32. if bit psc is set to logic 0, then the prescaler value is 31. one etu will last a number of card clock cycles equal to prescaler x pdr. all baud rates specified in iso 7816 norm are achievable with this configuration. table 14 uart con?guration register 2 (ucr21, 22 and 23) (read and write); address: 3 (all relevant bits are cleared after reset) table 15 baud rates with a 3.58 mhz card clock frequency (31;12 means prescaler set to 31 and pdr set to 12) pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 uc27 uc26 uc25 uc24 uc23 uc22 uc21 uc20 not used distbe/rbf disaux pdwn san a ut oconv cku psc d f 0123456910111213 1 31;12 9600 31;12 9600 31;18 6400 31;24 4800 31;36 3200 31;48 2400 31;60 1920 32;16 32;24 32;32 32;48 32;64 2 31;6 19200 31;6 19200 31;9 12800 31;12 9600 31;18 6400 31;24 4800 31;30 3840 32;8 32;12 32;16 32;24 32;32 3 31;3 38400 31;3 38400 31;6 19200 31;9 12800 31;12 9600 31;15 7680 32;4 32;6 32;8 32;12 32;16 4 31;3 38400 31;6 19200 32;2 32;3 32;4 32;6 32;8 5 31;3 38400 32;1 32;2 32;3 32;4 6 32;1 32;2 8 31;1 115200 31;1 115200 31;2 57600 31;3 38400 31;4 28800 31;5 23040 32;2 32;4 9 31;3 38400
2000 nov 09 17 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b for other baud rates than those given in table 15, there is the possibility to set bit cku (clock uart) to logic 1. in this case, the etu will last half of the formula given above. if bit autoconv is set, then the convention is set by software using bit conv in the uart configuration register. if it is reset, then the configuration is automatically detected on the first received character whilst the start session (ss) bit is set. synchronous/ asynchronous (san) is set by software if a synchronous card is expected. the uart is then bypassed, and only bit 0 in the urr and utr is connected to the i/o. in this case the clk is controlled by bit sc in the ccr. when power-down mode (pdwn) is set by software, the crystal oscillator is stopped. this mode allows low consumption in applications where it is required. during this mode, it is not possible to select another card other than the currently selected one. there are 5 ways of escaping from the power-down mode: 1. insert card 1 or card 2 2. withdraw card 1 or card 2 3. select the tda8007b by resetting cs (this assumes that the tda8007b had been deselected after setting power-down mode) 4. intauxl has been set due to a change on pin intaux 5. if cs is permanently set to low, reset bit pdwn by software. after any of these 5 events, the tda8007b will leave the power-down mode, and will pull int low when it is ready to communicate with the system microcontroller. the system microcontroller may then read the status registers, and int will return high (if the system microcontroller has woken the tda8007b by reselecting it, then no bits will be set in the status registers). if the disable aux (disaux) interrupt bit in ucr2 is set, then a change on intaux will not generate an interrupt (but bit intauxl in the hsr will be set; it is therefore necessary to read the hsr before a disaux reset to avoid an interrupt by intauxl). to avoid an interrupt during a change of card, it is better to set the disaux bit in ucr2 for both cards. if the disable tbe/rbf (distbe/rbf) interrupt bit is set, then reception or transmission of a character will not generate an interrupt: this feature is useful for increasing communication speed with the card; in this case, a copy of the tbe/rbf bit within the msr must be polled (and not the original) in order not to loose priority interrupts which can occur in the usr. the guard time register (see table 17) is used for storing the number of guard etus given by the card during atr. in transmission mode, the uart will wait this number of etus before transmitting the character stored in the utr. in t = 1 protocol, when gtr = ff means operation at 11 etus. in protocol t = 0, gtr = ff means operation at 12 etus. the uart configuration register (see table 18) is used for setting the parameters of the iso uart. the convention (conv) bit is set if the convention is direct. conv is either automatically written by hardware according to the convention detected during atr, or by software if the bit autoconv is set. the ss bit is set before atr for automatic convention detection and early answer detection (this bit must be reset by software after reception of a correct initial character). the last character to transmit (lct) bit is set by software before writing the last character to be transmitted in the utr. it allows automatic change to reception mode. it is reset by hardware at the end of a successful transmission. the transmit/receive (t/r) bit is set by software for transmission mode. a change from logic 0 to logic 1 will set bit tbe in the usr. bit t/r is automatically reset by hardware if the lct bit has been used before transmitting the last character. the protocol (prot) bit is set if the protocol type is asynchronous t = 1. if prot = 0, the protocol is t = 0. the flow control (fc) bit is set if flow control is used (not described in this specification). if the force inverse parity (fip) bit is set to high the uart will nak a correctly received character, and will transmit characters with wrong parity bits.
2000 nov 09 18 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b clock configuration register (see table 19): for cards 1 and 2, the ccr defines the clock for the selected card. for cards 1, 2 and 3 it defines the clock to the iso uart. it should be noted that if bit cku in the prescaler register of the selected card is set, then the iso uart is clocked at twice the frequency of the card, which allows baud rates not foreseen in iso 7816 norm to be reached. in case of an asynchronous card, the clock stop (cst) bit defines whether the clock to the card is stopped or not. if cst is set, then clk is stopped low if shl = 0, and high if shl = 1. if cst is reset, then clk is determined by bits ac0, ac1 and ac2; see table 16. all frequency changes are synchronous, thus ensuring that no spike or unwanted pulse widths occur during changes. table 16 clk value for an asynchronous card when switching from xtal/n to 1 2 f int or vice verse, only bit ac2 must be changed (ac1 and ac0 must remain the same). when switching from xtal/n or 1 2 f int to clk stop or vice verse, only bits cst and shl must be changed. when switching from xtal/n to 1 2 f int or vice verse, a maximum delay of 200 m s can occur between the command and the effective frequency change on clk (the fastest switching time is from 1 2 xtal to 1 2 f int or vice verse, the best for duty cycle is from 1 8 xtal to 1 2 f int or vice verse). it is necessary to wait the maximum delay time before reactivating from power-down mode. in the event of a synchronous card, then the clk contact is the copy of the value written in synchronous clock (sc). in reception mode, the data from the card is available to ur0 after a read operation of the urr; in transmission mode, the data is written on the i/o line of the card when the utr has been written to and remains unchanged when another card is selected. the power control register (pcr), see table 20: starts or stops card sessions. reads or writes on auxiliary card contacts c4 and c8. is available only for cards 1 or 2. if the microcontroller sets start to logic 1, then the selected card is activated (see section activation sequence). if the microcontroller resets start to logic 0, then the card is deactivated (see section deactivation sequence). start is automatically reset in case of emergency deactivation. if 3 v/5 v is set to logic 1, then v cc is 3 v. if 3 v/5 v is set to logic 0, then v cc is 5 v. when the card is activated, rst is the copy of the value written in rstin. if 1.8 v is set, then v cc = 1.8 v: it should be noted that no specification is guaranteed at this voltage. when writing to the pcr, c4 will output the value written to pcr4, and c8 the value written to pcr5. when reading from the pcr, pcr4 will store the value on c4, and pcr5 the value on c8. ac2 ac1 ac0 clk 000 1 2 xtal 001 1 2 xtal 010 1 4 xtal 011 1 8 xtal 100 1 2 f int 101 1 2 f int 110 1 2 f int 111 1 2 f int table 17 guard time register (gtr1, 2 and 3) (read and write); address: 5 (all bits are cleared after reset) table 18 uart con?guration register 1 (ucr11, 12 and 13) (read and write); address: 6 (all relevant bits are cleared after reset) gt7 gt6 gt5 gt4 gt3 gt2 gt1 gt0 gt7 gt6 gt5 gt4 gt3 gt2 gt1 gt0 uc7 uc6 uc5 uc4 uc3 uc2 uc1 uc0 not used fip fc prot t/r lct ss conv
2000 nov 09 19 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b table 19 clock con?guration register (ccr1, 2 and 3) (read and write); address: 1 (all bits are cleared after reset) table 20 power control register (pcr1 and 2) (read and write); address: 7 (all relevant bits are cleared after reset) table 21 register summary cc7 cc6 cc5 cc4 cc3 cc2 cc1 cc0 not used not used shl cst sc ac2 ac1 ac0 pcr7 pcr6 pcr5 pcr4 pcr3 pcr2 pcr1 pcr0 not used not used c8 c4 1v8 rstin 3v/5v start name addr r/w 7 6 543210 value at reset csr 00 r/w not used not used not used not used riu sc3 sc2 sc1 xxxx0000 hsr 0f r not used prtl2 prtl1 supl prl2 prl1 intaux l ptl x0010000 msr 0c r not used fe bgt not used pr2 pr1 intaux tbe/rf x10xxxx0 tor1 09 w tol7 tol6 tol5 tol4 tol3 tol2 tol1 tol0 00000000 tor2 0a w tol15 tol14 tol13 tol12 tol11 tol10 tol9 tol8 00000000 tor3 0b w tol23 tol22 tol21 tol20 tol19 tol18 tol17 tol16 00000000 toc 08 r/w toc7 toc6 toc5 toc4 toc3 toc2 toc1 toc0 00000000 utr 0d w ut7 ut6 ut5 ut4 ut3 ut2 ut1 ut0 00000000 urr 0d r ur7 ur6 ur5 ur4 ur3 ur2 ur1 ur0 00000000 fcr 0c w not used pec2 pec1 pec0 not used fl2 fl1 fl0 x000x000 usr 0e r to3 not used to1 ea pe ovr fer tbe/ rbf 0x000000 pdr 02 r/w pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 00000000 ucr2 03 r/w not used distbe /rbf disaux pdwn san a ut oc cku psc x0000000 gtr 05 r/w gt7 gt6 gt5 gt4 gt3 gt2 gt1 gt0 00000000 ucr1 06 r/w not used fip fc prot t/r lct ss conv x0000000 ccr 01 r/w not used not used shl cst sc ac2 ac1 ac0 00000000 pcr 07 r/w not used not used c8 c4 1v8 rstin 3v/5v start xx110000
2000 nov 09 20 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b supply the circuit operates within a supply voltage range of 2.7 to 6 v. the supply pins are v dd , v dda , gnd and agnd. pins v dda and agnd supply the analog drivers to the cards and have to be externally decoupled because of the large current spikes that the cards and the step-up converter can create. pins v dd and gnd supply the rest of the chip. an integrated spike killer ensures that the contacts to the cards remain inactive during power-up or power-down. an internal voltage reference is generated which is used within the step-up converter, the voltage supervisor and the v cc generators. the voltage supervisor generates an alarm pulse, whose length is defined by an external capacitor tied to pin delay, when v dd is too low to ensure proper operation (1 ms per 1 nf typical). this pulse may be used as a reset pulse by the system microcontroller (pin rstout, active high). it is also used in order to either block any spurious noise on card contacts during the microcontrollers reset, or to force an automatic deactivation of the contacts in the event of supply dropout (see sections activation sequence and deactivation sequence). after power-on, or after a voltage drop, bit supl is set within the hardware status register (hsr) and remains set until hsr is read-out outside the alarm pulse. pin int is low for the duration that rstout is active. if needed, a complete reset of the chip may be performed by discharging the capacitor c delay . handbook, full pagewidth v th1 v dd v th2 c delay rstout supl int supply dropout power-off reset by c delay power-on status read fce683 t w fig.7 voltage supervisor.
2000 nov 09 21 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b step-up converter except for the v cc generator and the other cards contacts buffers, the whole circuit is powered by v dd , and v dda . if the supply voltage is 2.5 v, then a higher voltage is needed for the iso contacts supply. when a card session is requested by the microcontroller, the sequencer first enables the step-up converter (a switched capacitors type) which is clocked by an internal oscillator at a frequency of approximately 2.5 mhz. suppose that v cc is the maximum of v cc1 and v cc2 , then there are four possible situations: 1. v dd = 3 v and v cc = 3 v: in this case the step-up converter acts as a doubler with a regulation of approximately 4.0 v. 2. v dd = 3 v and v cc = 5 v: in this case the step-up converter acts as a tripler with a regulation of approximately 5.5 v. 3. v dd = 5 v and v cc = 3 v: in this case the step-up converter acts as a follower: v dd is applied to v up . 4. v dd = 5 v and v cc = 5 v: in this case the step-up converter acts as a doubler with a regulation of approximately 5.5 v. the recognition of the supply voltage is done by the tda8007b at approximately 3.5 v. the output voltage v up is fed to the v cc generators. v cc and gnd are used as a reference for all other card contacts. iso 7816 security the correct sequence during activation and deactivation of the cards is ensured by two specific sequencers, clocked by a division ratio of the internal oscillator. activation (start bit high in pcr1 or pcr2) is only possible if the card is present (pres active high with an internal current source to gnd) and if the supply voltage is correct (supervisor not active). the presence of the cards is signalled to the microcontroller by the hardware status register (hsr). bits pr1 or pr2 (in the usr) are set if card 1 or card 2 is present. prl1 or prl2 are set if pr1 or pr2 has toggled. during a session, the sequencer performs an automatic emergency deactivation on one card in the event of card take-off, or short-circuit. both cards are automatically deactivated in the event of a supply voltage drop, or overheating. the hardware status register is updated and the int line falls, so that the system microcontroller is aware of what happened. activation sequence when the cards are inactive, v cc , clk, rst, c4, c8 and i/o are low, with low-impedance with respect to gnd. the step-up converter is stopped. when everything is satisfactory (voltage supply, card present and no hardware problems), the system microcontroller may initiate an activation sequence on a present card. after selecting the card and leaving the uart reset mode, and then configuring the necessary parameters for the counters and the uart, the start bit can be set within the pcr (t 0 ) (see fig.8): the step-up converter is started (t 1 ); if one card was already active, then the step-up converter was already on and nothing more occurs at this step v cc starts rising (t 2 ) from 0 to 5 v or 3 v with a controlled rise time of 0.17 v/ m s (typ.) i/o rises to v cc (t 3 ); c4 and c8 also rise if bits c4 and c8 within the pcr have been set to logic 1 (integrated 10 k w pull-up resistors to v cc ) the clk is sent to the card and rst is enabled (t 4 ). after a number of clk pulses that can be counted with the time-out counter, bit rstin may be set by software: rst will then rise to v cc . the sequencer is clocked by 1 64 f int which leads to a time interval of t = 25 m s (typ.). thus t 1 =0to 1 64 t, t 2 =t 1 + 3 2 t, t 3 =t 1 + 7 2 t and t 4 =t 1 + 4t. deactivation sequence when the session is completed, the microcontroller resets start high (t 10 ). the circuit then executes an automatic deactivation sequence (see fig.9): the card is reset (rst falls low) (t 11 ) the clk is stopped (t 12 ) i/o, c4 and c8 fall to 0 v (t 13 ) v cc falls to 0 v with typical 0.17 v/ m s slew rate (t 14 ) the step-up converter is stopped and clk, rst, v cc and i/o become low-impedance to gnd (t 15 ) (if both cards are inactive). t 11 =t 10 + 1 64 t, t 12 =t 11 + 1 2 t, t 13 =t 11 +t,t 14 =t 11 + 3 2 t and t 15 =t 11 + 7 2 t. t de = time that v cc needs to decrease to less than 0.4 v.
2000 nov 09 22 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b handbook, full pagewidth start v up v cc i/o rstin clk rst t 0 t 2 t 3 t 4 = t act at r t 1 fce684 fig.8 activation sequence. handbook, full pagewidth start v up v cc i/o clk rst t 10 t 12 t 13 t de t 14 t 15 t 11 fce685 fig.9 deactivation sequence.
2000 nov 09 23 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b limiting values in accordance with the absolute maximum rating system (iec 60134). handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices. thermal characteristics symbol parameter conditions min. max. unit v dda analog supply voltage - 0.5 +6.5 v v dd supply voltage - 0.5 +6.5 v v n input voltage on all pins except s1, s2, s3, s4 and v up - 0.5 v dd + 0.5 v input voltage on pins s1, s2, s3, s4 and vup - 0.5 +7.5 v i n1 dc current into all pins except s1, s2, s3, s4 and v up - 5+5 ma i n3 dc current from or to pins s1, s2, s3, s4 and v up - 200 +200 ma p tot total power dissipation t amb = - 20 to +85 c - 700 mw t stg ic storage temperature - 55 +150 c t j junction temperature - 125 c v es electrostatic discharge voltage on pins i/o1, v cc1 , rst1, clk1, gndc1, pres1, i/o2, v cc2 , rst2, clk2, gndc2 and pres2 - 6+6 kv on pins c41, c42, c81 and c82 - 5.5 +5.5 kv on pins d0 to d7 - 1.8 +1.8 kv on other pins - 2+2 kv symbol parameter conditions value unit r th(j-a) from junction to ambient in free air 78 k/w
2000 nov 09 24 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b characteristics v dd = 3.3 v; v ss =0v; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies v dd supply voltage 2.7 - 6.0 v i dd(pd) supply current in power-down mode v dd = 3.3 v; cards inactive; xtal oscillator stopped -- 350 m a v dd = 3.3 v; cards active at v cc = 5 v; clk stopped; xtal oscillator stopped -- 3ma i dd(sm) supply current in sleep mode both cards powered, but with clk stopped -- 5.5 ma i dd(om) supply current in operating mode i cc1 = 65 ma; i cc2 = 15 ma; f xtal = 20 mhz; f clk = 10 mhz; 5 v cards; v dd = 2.7 v -- 315 ma i cc1 = 50 ma; i cc2 = 30 ma; f xtal = 20 mhz; f clk = 10 mhz; 3 v cards; v dd = 2.7 v -- 215 ma i cc1 = 50 ma; i cc2 = 30 ma; f xtal = 20 mhz; f clk = 10 mhz; 3 v cards; v dd =5v -- 100 ma v th1 threshold voltage on v dd (falling) 2.25 - 2.50 v v hys1 hysteresis on v th1 50 - 170 mv v th2 threshold voltage on pin delay - 1.25 - v v delay voltage on pin delay -- v dd + 0.3 v i o(delay) output current at pin delay pin grounded (charge) -- 2 -m a v delay =v dd (discharge) - 2 - ma c delay capacitance value 1 -- nf t w(alarm) alarm pulse width c delay =22nf - 10 - ms rstout (open-drain active high output) i oh high-level output current active low option; v oh =5v -- 10 m a v ol low-level output voltage active low option; i ol =2ma - 0.3 - +0.4 v i ol low-level output current active high option; v ol =0v --- 10 m a v oh high-level output voltage active high option; i oh = - 1 ma 0.8v dd - v dd + 0.3 v crystal oscillator f xtal crystal frequency 4 - 25 mhz f ext external frequency applied to pin xtal1 0 - 25 mhz
2000 nov 09 25 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b step-up converter f int oscillation frequency 2 2.5 3.7 mhz v vup voltage on pin v up at least one 5 v card - 5.7 - v both cards 3 v - 4.1 - v v det(dt) detection voltage for doubler/tripler selection 3.4 3.5 3.6 v reset output to the cards (rst1 and rst2) v o(inactive) output voltage in inactive mode no load 0 - 0.1 v i inactive =1ma 0 - 0.3 v i rst(inactive) current from pin rst when inactive and pin grounded 0 -- 1ma v ol low-level output voltage i ol = 200 m a0 - 0.3 v v oh high-level output voltage i oh = - 200 m av cc - 0.7 - v cc v t r rise time c l =30pf -- 0.1 m s t f fall time c l =30pf -- 0.1 m s clock output to the cards (clk1 and clk2) v o(inactive) output voltage in inactive mode no load 0 - 0.1 v i inactive =1ma 0 - 0.3 v i clk(inactive) current from pin clk when inactive and pin grounded 0 -- 1ma v ol low-level output voltage i ol = 200 m a0 - 0.3 v v oh high-level output voltage i oh = - 200 m av cc - 0.5 - v cc v t r rise time c l =30pf -- 8ns t f fall time c l =30pf -- 8ns f clk clock frequency 1 mhz idle con?guration 1 - 1.85 mhz operational 0 - 10 mhz d duty factor c l =30pf 45 - 55 % sr slew rate (rise and fall) c l = 30 pf 0.2 -- v/ns symbol parameter conditions min. typ. max. unit
2000 nov 09 26 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b card supply voltage (v cc1 and v cc2 ) (2 ceramic multilayer capacitors with low esr of minimum 100 nf should be used in order to meet these speci?cations) v o(inactive) output voltage in inactive mode no load 0 - 0.1 v i inactive =1ma 0 - 0.3 v i vcc(inactive) current from pin v cc when inactive and pin grounded --- 1ma v cc output voltage active mode; i cc <65ma; 5 v card 4.75 5 5.25 v active mode; i cc <50ma; 3 v card 2.78 3 3.22 v active mode; current pulses of 40 nc with i < 200 ma; t < 400 ns; f < 20 mhz; 5 v card 4.6 - 5.4 v active mode; current pulses of 24 nc with i < 200 ma; t < 400 ns; f < 20 mhz; 3 v card 2.75 - 3.25 v i cc output current 3 v card; from 0 to 3 v --- 50 ma 5 v card; from 0 to 5 v --- 65 ma sr slew rate up or down; maximum capacitance = 300 nf 0.05 0.16 0.22 v/ m s i cc1 +i cc2 sum of both cards current --- 80 ma data lines (i/o1 and i/o2) (i/o1 has an integrated 10 k w pull-up at v cc1 and i/o2 at v cc2 ) v o(inactive) output voltage in inactive mode no load 0 - 0.1 v i inactive =1ma -- 0.3 v i o(inactive) current from i/o when inactive and pin grounded --- 1ma v ol low-level output voltage i/o con?gured as an output; i ol =1ma 0 - 0.3 v v oh high-level output voltage i/o con?gured as an output; i oh < - 40 m a 0.8v cc - v cc + 0.25 v v il low-level input voltage i/o con?gured as an input - 0.3 - +0.8 v v ih high-level input voltage i/o con?gured as an input 1.5 - v cc v i il low-level input current on i/o v il =0 -- 600 m a i li(h) input leakage current high on i/o v ih =v cc -- 20 m a t i(tr) , t i(tf) input transition times c l < = 30 pf -- 1 m s t o(tr) , t o(tf) output transition times c l < = 30 pf -- 0.1 m s r pu internal pull-up resistance between i/o and v cc 81012k w symbol parameter conditions min. typ. max. unit
2000 nov 09 27 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b auxiliary cards contacts (pins c41, c81, c42 and c82) (pins c41 and c81 have an integrated 10 k w pull-up at v cc1 , pins c42 and c82 have an integrated 10 k w pull-up at v cc2 ) v o(inactive) output voltage inactive no load 0 - 0.1 v i inactive =1ma -- 0.3 v i inactive current from pins c4 or c8 when inactive and pin grounded --- 1ma v ol low-level output voltage c4 or c8 con?gured as an output; i ol =1ma 0 - 0.3 v v oh high-level output voltage i/o con?gured as an output; i oh < - 40 m a 0.8v cc - v cc + 0.25 v v il low-level input voltage c4 or c8 con?gured as an input - 0.3 - +0.8 v v ih high-level output voltage c4 or c8 con?gured as an input 1.5 - v cc v i il low-level input current on pins c4 or c8 v il =0 -- 600 m a i li(h) input leakage current high on pins c4 or c8 v ih =v cc -- 20 m a t i(tr) , t i(tf) input transition times c l =30pf -- 1 m s t o(tr) , t o(tf) output transition times c l =30pf -- 0.1 m s t w(pu) width of active pull-up pulse - 200 - ns r int(pu) internal pull-up resistance between c4/c8 and v cc 81012k w f (max) maximum frequency on c4 or c8 -- 1 mhz timing t act activation sequence duration -- 130 m s t de deactivation sequence duration -- 150 m s protections and limitations i cc(sd) shutdown and limitation current at v cc -- 100 - ma i i/o(lim) limitation current on the i/o - 15 - +15 ma i clk(lim) limitation current on pin clk - 70 - +70 ma i rst(sd) shutdown and limitation current on rst - 20 - +20 ma t sd shutdown temperature - 150 - c card presence inputs 1s (pins pres1 and pres2) v il low-level input voltage -- 0.3v dd v v ih high-level input voltage 0.7v dd -- v i il(l) input leakage current low v in =0 - 20 - +20 m a i il(h) input leakage current high v in =v dd - 20 - +20 m a symbol parameter conditions min. typ. max. unit
2000 nov 09 28 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b bidirectional data bus (pins d0 to d7) v il low-level input voltage -- 0.3v dd v v ih high-level input voltage 0.7v dd -- v i il(l) input leakage current low - 20 - +20 m a i il(h) input leakage current high - 20 - +20 m a c l load capacitance -- 10 pf v ol low-level output voltage i ol =5ma -- 0.2v dd v v oh high-level output voltage i oh = - 5 ma 0.8v dd -- v t o(tr) , t o(tf) output transition time c l =50pf -- 25 ns logic inputs (pins ale, a0, a1, a2, a3, intaux, cs, rd and wr) v il low-level input voltage - 0.3 - +0.3v dd v v ih high-level input voltage 0.7v dd - v dd + 0.3 v i il(l) input leakage current low - 20 - +20 m a i il(h) input leakage current high - 20 - +20 m a c l load capacitance -- 10 pf auxiliary i/o (pin i/oaux) v il low-level input voltage - 0.3 - +0.3v dd v v ih high-level input voltage 0.7v dd - v dd + 0.3 v i il(h) input leakage current high - 20 - +20 m a i il low-level input current v il =0 --- 600 m a v ol low-level output voltage i ol =1ma -- 300 mv v oh high-level output voltage i oh =40 m a 0.8v dd - v dd +0.25 v r int(pu) internal pull-up resistance between i/oaux and v dd 81012k w t i(tr) , t i(tf) input transition time c l =30pf -- 1 m s t o(tr) , t o(tf) output transition time c l =30pf -- 0.1 m s f i/oaux(max) maximum frequency on pin i/oaux -- 1 mhz interrupt line int (open-drain active low output) v oh low-level output voltage i oh =2ma -- 0.3 v i il(h) input leakage current high -- 10 m a symbol parameter conditions min. typ. max. unit
2000 nov 09 29 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b timing for multiplexed bus; see fig.4 t xtal1 period on xtal1 50 -- ns t w(ale) ale pulse width 20 -- ns t avll address valid to ale low 10 -- ns t (al - rwl) ale low to rd or wr low 10 -- ns t w(rd) rd pulse width for urr 2t xtal1 -- ns pulse width for other registers 10 -- ns t (rl - dv) rd low to data out valid -- 50 ns t (rwh - ah) rd or wr high to ale high 10 -- ns t w(wr) wr pulse width 10 -- ns t (dv - wl) data in valid to wr low 10 -- ns timing for non-multiplexed bus; see fig.5 t (reh - cl) rd or en high to cs low 10 -- ns t (cel - dv) cs and en low to data out valid when reading from urr; t (cel - dv) is minimum 2t xtal1 -- 50 ns t (ceh - dz) cs and en high to data high-impedance -- 10 ns t (ad - dv) addresses stable to data out valid -- 10 ns t (rl - cel) r/ w low to cs or en low 10 -- ns t (crel - dz) cs and r/ w and en low to data in high-impedance --- ns t (dv - wl) data valid to wr low 10 -- ns symbol parameter conditions min. typ. max. unit
2000 nov 09 30 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... application information: handbook, full pagewidth rstout c14 i/oaux i/o1 c81 pres1 c41 tda8007b ic1 89c51 p0(7:0) gndc1 clk1 v cc1 rst1 i/o2 c82 1 2 3 4 5 6 7 8 9 10 11 12 c8 rd d7 d6 d5 d4 d3 d2 d1 d0 v dd sam agnd 36 35 34 33 32 31 30 29 28 v ss xtal1 20 19 xtal2 18 p3.7 17 p3.6 16 p3.5 15 p3.4 14 p3.3 13 p3.2 12 p3.1 11 p3.0 10 rst 9 p1.7 8 p1.6 7 p1.5 6 p1.4 5 p1.3 4 p1.2 3 p1.1 2 p1.0 tx rx 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 p2.0 tp20 wr tp18 ale p2.1 21 22 p2.2 23 p2.3 24 p2.4 25 p2.5 26 p2.6 27 p2.7 28 lpsen 29 ale 30 lea 31 p0.7 32 p0.6 33 p0.5 34 p0.4 35 p0.3 36 p0.2 37 p0.1 38 p0.0 39 v cc 40 27 26 25 tp51 gnd pres2 c42 gndc2 clk2 v cc2 rst2 gnd v up sap sbp v dda sbm 13 14 15 16 17 18 19 20 21 22 23 24 delay xtal1 xtal2 ad0 ad1 ad2 ad3 intaux int ale cs wr 48 47 46 45 44 43 42 41 40 39 38 37 22 pf c23 c27 100 nf r4 100 k w r3 0 w r2 0 w tp8 tp4 + 5 v gnd 3 v or 5 v gnd c18 100 nf c19 100 nf c24 100 nf c26 100 nf c13 100 nf c22 100 nf c1 10 m f 16 v 100 nf c25 100 nf 100 nf c15 v dd v dd v dd v dd v dd v dd r1 100 k w v dd y2 22 pf c7 c6 c5 c11 c21 c31 c41 k1 k2 c4 card_read_lm01 u6 c3 c2 c1 c51 c61 c71 c81 c8 c17 100 nf c7 c6 c5 c11 c21 c31 c41 k1 k2 c4 card_read_lm01 u5 card 1 card 2 c3 c2 c1 c51 c61 c71 c81 tp22 int tp23 cs 8007b c16 fce690 c12 100 nf c3 33 m f 16 v v dd 10 m f 16 v c2 j1 1 j1 2 fig.10 application diagram.
2000 nov 09 31 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b package outline unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.60 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 99-12-27 00-01-19 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 q a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
2000 nov 09 32 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2000 nov 09 33 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable
2000 nov 09 34 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b data sheet status note 1. please consult the most recently issued data sheet before initiating or completing a design. data sheet status product status definitions (1) objective speci?cation development this data sheet contains the design target or goal speci?cations for product development. speci?cation may change in any manner without notice. preliminary speci?cation quali?cation this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. product speci?cation production this data sheet contains ?nal speci?cations. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2000 nov 09 35 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b notes
? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 2000 70 philips semiconductors C a worldwide company for all other countries apply to: philips semiconductors, marketing communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 3 figtree drive, homebush, nsw 2140, tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, via casati, 23 - 20052 monza (mi), tel. +39 039 203 6838, fax +39 039 203 6800 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland : al.jerozolimskie 195 b, 02-222 warsaw, tel. +48 22 5710 000, fax. +48 22 5710 001 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 5f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2451, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 60/14 moo 11, bangna trad road km. 3, bagna, bangkok 10260, tel. +66 2 361 7910, fax. +66 2 398 3447 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 208 730 5000, fax. +44 208 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 3341 299, fax.+381 11 3342 553 printed in the netherlands 753504/03/pp 36 date of release: 2000 nov 09 document order number: 9397 750 07619

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